招聘信息分享
JOBHUNTER
聚合各大厂 / 国企官网招聘信息，实时同步官方数据
招聘信息分享
JOBHUNTER
聚合各大厂 / 国企官网招聘信息，实时同步官方数据
1、负责影视制作链路AIGC相关产品设计与落地，推动内容制作全流程降本增效； 2、跟进影视制作行业发展趋势和AIGC新兴技术，与算法研发、业务团队紧密合作，规划产品发展方向。
1. 主导产品需求到芯片架构的全流程转化，基于产品定义规格书完成系统级架构设计，输出完整的SoC架构方案（含计算/控制/存储子系统、总线架构、电源域划分、封装策略等） 2. 负责SoC微架构设计，包含时钟树网络优化、电源域隔离策略、片上内存一致性协议设计（MESI/CC-NUMA等）、高速接口协议优化 3. 主导低功耗架构设计（DVFS/电源门控） 4. 构建系统级仿真平台，包括性能和功耗仿真模型，支持架构可行性验证和优化迭代，获得功耗/面积/性能（PPA）的最优平衡，同时支持芯片设计和系统验证 5. 开展竞品技术解构与竞争力分析，制定SoC架构差异化技术路线 6. 负责SOC架构团队的管理和人才建设，项目规划，方案制定和执行
1. 组建并高效管理SoC设计与验证团队，制定交付策略与计划，保障项目里程碑达成 2. 主导SoC前端设计与验证交付，攻克技术难题，确保高质量和高效产出 3. 优化SoC设计与验证流程，建立高效协作机制；跨团队协作与资源统筹，保障芯片开发周期资源高效调配 4. 指导团队解决设计、验证工作中的复杂问题（如低功耗设计、时序收敛、验证覆盖率提升） 5. 负责团队的管理和人才建设，能力建设（包括设计和研制先进方法学），项目规划，方案制定和执行
1. 参与模拟IP和各类PHY系统的验证工作，包括但不限于VCS前仿，后仿，数模混合仿真，以及设计参考模型。 2. 参与RFID，PLL, DDR,HBM, SERDES等PHY系统的debug。 3. 总结数模混合系统的验证经验，设计自动化验证脚本和编写相关VIP。
1. 组建并高效管理SoC设计团队，制定交付策略与计划，保障项目里程碑达成； 2. 主导SoC前端设计交付，攻克技术难题，确保高质量和高效产出； 3. 优化SoC设计流程，建立高效协作机制；跨团队协作与资源统筹，保障芯片开发周期资源高效调配； 4. 指导团队解决设计工作中的复杂问题（如微架构设计、低功耗设计、PPA优化、时序收敛、验证覆盖率提升）； 5. 负责团队的管理和人才建设，能力建设（包括设计先进方法学），项目规划，方案制定和执行。
1. 参与模拟IP和各类PHY系统的验证工作，包括但不限于VCS前仿，后仿，数模混合仿真，以及设计参考模型。 2. 参与RFID，PLL, DDR,HBM, SERDES等PHY系统的debug。 3. 总结数模混合系统的验证经验，设计自动化验证脚本和编写相关VIP。
1、作为内控接口人，协助所负责业务和职能团队制定或评估完善各项业务制度与流程，确保业务符合外部法规及公司要求。 2、通过业务及财务数据分析、调研等方式，快速识别和定位业务及财务风险，制定风险管控方案，并推动管理动作落地。3、参与构建风险监测指标体系，形成系统性数据监测方案，实现风险的持续动态监测与评估。 4、独立执行内控专项，深入识别业务设计及执行层面的风险及控制缺陷，提出改进建议并协同各方改善 5、参与风险事件应急处理、复盘，并跟踪改进方案落地。
Customer Relationship Building and Business Opportunity Development •Proactively analyze key industries within the assigned country/market, identify key or potential customers, and independently map out the customer’s decision-making chain to uncover real needs. •Engage customers using their business language to build trust, uncover product and technical requirements, and convert those requirements into qualified sales opportunities. •Drive upsell and cross-sell initiatives with existing customers, enhance their experience across service and business collaboration, accelerate cloud resource consumption. •Maintain regular contact with both existing and prospective customers to stay informed of their business strategies, budget cycles, vendor landscape, organizational structure, and technical environment. Product and Technical Value Communication •Leverage in-depth understanding of the customer’s industry and business context to help them recognize the technical value of Alibaba Cloud’s core offerings — including the Apsara Cloud Operating System, the “7 Core Products” and AI/Intelligent Computing solutions — while clearly articulating Alibaba Cloud’s differentiated competitive advantages over rival providers, reinforcing its positioning as the customer’s optimal strategic partner. •Independently deliver presentations to customers on Alibaba Cloud’s standardized product solutions; or, with support from Solutions Architects (SA), independently articulate tailored solutions aligned with the customer’s specific business scenarios — clearly communicating the competitive advantages of Alibaba Cloud’s offerings and the concrete business value they enable for the customer. Drive Decision-Making and Opportunity Conversion • Drive rapid customer decision-making and sustained adoption of Alibaba Cloud products and technical solutions through effective resource integration and strategic engagement — ensuring continuous value delivery to the customer. • Employ a full range of sales strategies — including persuasive communication, commercial negotiation, and tailored pricing proposals — to convert opportunities into closed deals, achieving performance targets while fostering mutually beneficial outcomes with customers. • Proactively identify and escalate customer experience issues encountered during product usage, driving internal cross-functional collaboration to resolve them — thereby catalyzing improvements in Alibaba Cloud’s product solutions, service delivery, and operational processes. Business Support •Provide end-to-end business support throughout the customer lifecycle by coordinating cross-functional resources to ensure successful project implementation, and proactively identifying and resolving product usage issues in a timely manner. •Accelerate the iterative adoption and optimization of Alibaba Cloud products on the customer side to effectively support the achievement of their technical objectives.
1、根据公司对药品类目的定位，对所负责品类制定年度、月度的品类计划，与运营营销等团队成员协同合作，完成业绩目标。 2、负责类目品牌的沟通谈判，结合运营及营销需求，整合双方资源，做好客情维护，保持良好合作关系。 3、根据市场变化，商品的价格波动，保证供价合理性，控制采购成本。 4、拓展优秀供应商，保证货源供给稳定性。
1. 负责阿里国际站海外买家召回与生命周期产品线的整体规划与迭代，围绕新客激活、活跃提升、沉默唤醒、流失挽回等关键节点，搭建覆盖全生命周期的召回产品能力，为买家活跃、留存与 GMV 增量结果负责。 2. 基于买家行为、交易、偏好等多维数据建设全生命周期用户画像，主导用户分层模型与场景化召回策略的产品化落地，让不同价值、不同阶段、不同意图的买家都能获得匹配的召回体验。 3. 统筹 PUSH、EDM、WhatsApp、站内信等触达渠道的产品能力建设，设计触达节奏、频次控制、疲劳度管理、跨渠道协同等核心模块，实现高效且体验友好的用户触达。 4. 作为产品负责人，牵头需求评审、方案设计、排期推进、上线验收全流程，与算法、工程、运营、设计、UED 高效协作，把复杂的召回策略沉淀为稳定、可复用的产品资产。 5. 持续跟踪跨境电商、用户增长、CRM 领域的行业动态与竞品策略，探索新的召回场景、触达形式与增长杠杆，保持产品的领先性。
In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.
As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to: · Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc. · Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan · Engaging closely with front-end power team on power estimation and fullchip power budgeting · Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables · Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks · Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff · Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule · Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin · Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective
As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to: · Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc. · Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan · Engaging closely with front-end power team on power estimation and fullchip power budgeting · Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables · Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks · Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff · Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule · Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin · Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective
盒马，新零售业态的新生力量，依靠科技重构餐饮及零售产业链。从创立伊始，盒马的使命就是让消费者享受“购新鲜”的品质生活。 盒马，以吃和吃的配套商品品类为切入，探索一条立足本地，深耕供应链与物流配送，线上线下融合，主打会员心智的全新电商道路， 让每一位盒马会员“吃的好， 吃的方便，吃的开心” 盒马，已打造了颇具人气的独立APP、业界名厨领衔的餐饮研发中心、国际标准的中央厨房、买手制采购团队、自建+众包物流配送体系和线下体验门店，从而形成了极致的配送“29分半”和产品“新鲜每一刻”这两大核心竞争力，如今盒马在消费者当中已形成了出色的口碑和网红效应，异军突起！ 欢迎有梦想的你，速速加入盒马！ 盒马官网：www.freshhema.com 【需要你具备】 1、本科及以上学历； 2、具备5年以上快消品或者零售业人力资源从业经验，其中至少3年以上管理经验； 3、有处理过劳工关系案例的经验； 4、具备与基层员工沟通的技巧； 5、有零售业新开店经验优先； 6、具备良好的团队意识、沟通能力及抗压能力；
In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.
职位描述： 1、游戏内的各类系统策划案撰写以及具体开发落地。 2、与美术，程序充分沟通，确保功能可行性和制定最终实现方案，对最终的游戏体验负责。 3、对系统功能的线上数据进行分析，并能根据实际数据结果总结并提出优化迭代建议。 4、输出规范的系统设计文档、流程图及验收标准，确保开发效率。 5、参与世界观设计，确保系统内容与游戏整体调性一致。
天猫淘宝海外，背靠淘宝数十亿商品，结合不同海外市场挖掘消费需求，为海外消费者提供精准、个性化的购物体验。 供给运营技术团队，负责天猫淘宝海外商家商品运营与管理，贯穿趋势洞察、标签沉淀、质量提优、前台投放与分销的完整运营链路。 我们深耕大模型技术，构建多智能体架构体系，助力业务建设高效的AI供给运营能力，解决在不同海外市场下，消费需求与淘宝海量商品之间的精准匹配问题，为海外消费者提供精准且有质感的购物体验。在这里，你能深入AI商业应用场景，将所学理论转化为实战成果，在电商AI赛道实现自我价值。诚邀有梦想、有热情、有实力的技术达人加入，共探AI赋能商家经营的无限可能！ 1、负责电商领域AI相关产品的全流程开发，包括但不限于大模型 Agent 应用的架构设计、工程实现、系统部署及迭代优化； 2、参与大模型技术在多场景解决方案中的落地实施，开展技术攻关与效果验证，推动 AI 能力在商业化场景的价值转化； 3、主导/参与大模型应用开发和技术中台建设，持续优化系统架构的高可用性、可扩展性及服务稳定性； 4、探索前沿技术落地可能性，参与技术决策并推动关键技术预研，构建企业大模型应用技术生态； 5、协同运营、产品、设计等协同团队共同完成复杂项目的技术方案设计与实施。
1. 负责芯片的测试NPI导入和量产管理，协同研发和ATE开发团队制定量产测试策略，实现高覆盖率、低成本且具备可制造性的量产测试方案，确保从 NPI 到 MP 阶段的平稳过渡； 2. 主导 ATE 测试程序与 SLT 测试系统的量产导入与维护，监控并优化测试良率及稳定性，通过硬件和方案优化提升良率并降低测试成本； 3. 负责量产测试数据的实时监控与分析，建立良率预警机制，针对 ATE/SLT 低良率、误测或生产异常进行根因分析，并协调资源快速解决量产问题； 4. 负责量产扩产相关的OSAT/Tester/测试tooling的Correlation 5. 管理量产测试资源与供应链，包括 ATE 机台、Prober/Handler、Loadboard/Probe Card 等硬件资源的选型、DOE设计、验收、维护及生命周期管理，以及OSAT在 ATE/SLT 环节的技术审核与产能协调； 6. 构建和完善 ATE/SLT 量产测试管理体系和数据分析方法，制定标准化作业程序及技术规范，推动测试自动化与数据闭环建设，确保量产测试质量符合公司标准及客户要求；
1、根据芯片产品规格与测试需求，与芯片/光学设计人员、产品经理合作，负责制定CPO/NPO与硅光产品有竞争力的、高质量低成本的量产 ATE 测试方案，覆盖EIC/PIC和OE集成模块。 2、根据测试方案，在相应 ATE 平台上开发软/硬件测试系统，含电测试资源与光子子系统（光源、光路对准/耦合、光功率与光谱测量），并导入测试厂/光子封测厂支撑大批量量产。 3、制定并实施CPO/NPO ATE characterization 测试方案，摸底器件的光/电特性，从覆盖率、精度与测试时间上优化测试程序。 4、构建晶圆级光学探针测试与模块级光I/O/光纤阵列耦合测试能力；推动自动光路对准及主动/被动对准策略，实现稳定、高通量的量产测试。 5、协助产品工程师制定光器件及模块的可靠性测试方案，支撑可靠性测试的筛选与回测，确保芯片质量。 6、收集并分析量产测试数据（良率/datalog），负责量产测试维护，针对电参数与光参数的低良分析、事故处理等
1. 负责阿里云资产运营的复杂业务模式设计，输出业务蓝图（含供应关系、资产权属流转、交付形态、账务对账等）及系统落地方案，明确业务模式、平台关键里程碑与验收标准、节奏，推动各方按业务承诺时间完成上线 2. 主导跨领域方案设计与落地推动，覆盖上游联合供应链、到货计划、现场交付、资产运营与现场资产运维、财务对账等业务领域及十余类系统，界定各领域改造范围、领域边界与数据口径，联合各领域产品负责人完成方案评审、排期对齐与风险管控。 3. 负责业务的 AI 化规划与落地，制定AI 应用路径与效能目标，在新模式方案设计中明确AI 与 Agent 承接边界，人机协同流程与安全护栏设计、评测集与效果回归机制建设。 4. 负责平台增量能力的建设与沉淀，评估新模式下存量能力的复用范围及需新建的能力，将供应关系、资产权属结构、交付形态与成本归属等差异收敛为可配置的领域模型、业务规则与流程编排，形成标准化接入方案，推动新模式由全链路改造向配置化接入演进。 5. 联合业务运营团队构建治理与度量机制，实现策略、规则、红线、抽检及审计能力的产品化；建立新模式上线周期、改造工作量、账实差异率、对账自动匹配率、AI 人力替代效能等核心指标体系，支撑持续迭代与复盘。